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april 2009 doc id 15596 rev 1 1/31 31 lis33de mems motion sensor 3-axis - 2g/8g smart digital output ?nano? accelerometer features 2.16 v to 3.6 v supply voltage 1.8 v compatible ios < 1 mw power consumption 2g/ 8g dynamically selectable full-scale i 2 c/spi digital output interface programmable interrupt generator embedded self test 10000g high shock survivability ecopack? rohs and ?green? compliant (see section 8 ) applications portrait - landascape im age rotation in mobile phones and pda motion activated user interfaces gaming motion triggered wake-up description the lis33de is an ultra compact low-power three axis linear accelerometer belonging to the ?nano? family of st motion sensors. it includes a sensing element and an ic interface able to provide the measured acceleration to the external world through i 2 c/spi serial interface. the sensing element is manufactured using a dedicated process developed by st to produce inertial sensors and actuators in silicon. the ic interface is manufactured using a cmos process that allows to design a dedicated circuit which is trimmed to better match the sensing element characteristics. the lis33de has dynamically user selectable full scales of 2g/ 8g and it is capable of measuring accelerations with an output data rate of 100 hz or 400 hz. a self-test capability allows the user to check the functioning of the sensor in the final application. the device may be configured to generate inertial wake-up/free-fall interrupt signals when a programmable acceleration threshold is crossed at least in one of the three axis. thresholds and timing of interrupt generator are programmable by the end user on the fly. the lis33de is available in plastic thin land grid array package (lga) and it is designed to operate over an extended temperature range from -40c to +85c. lga 16 (3x3x1mm 3 ) table 1. device summary order code temp range, cpackage packing lis33de -40 to +85 lga 16 tray LIS33DETR -40 to +85 lga 16 tape and reel www.st.com
contents lis33de 2/31 doc id 15596 rev 1 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3.1 spi - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3.2 i2c - inter ic control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.5 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.5.1 sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.5.2 zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.5.3 self test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 ic interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1 i2c serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.1 i2c operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2 spi bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2.1 spi read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2.2 spi write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2.3 spi read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
lis33de contents doc id 15596 rev 1 3/31 7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.1 ctrl_reg1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.2 ctrl_reg2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.3 ctrl_reg3 [interrupt ctrl register] (22h) . . . . . . . . . . . . . . . . . . . . . . 23 7.4 status_reg (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.5 out_x (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.6 out_y (2bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.7 out_z (2dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.8 ff_wu_cfg (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.9 ff_wu_src (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.10 ff_wu_ths (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.11 ff_wu_duration (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
list of tables lis33de 4/31 doc id 15596 rev 1 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. mechanical characteristics @ vdd=2.5v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. electrical characteristics @ vdd=2.5v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 5. spi slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 6. i2c slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 7. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 8. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 9. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 10. transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 11. transfer when master is writing multiple bytes to slave:. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 12. transfer when master is receiving (reading) one byte of data from slave: . . . . . . . . . . . . . 17 table 13. transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 17 table 14. transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 18 table 15. register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 16. ctrl_reg1 (20h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 17. ctrl_reg1 (20h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 18. ctrl_reg2 (21h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 19. ctrl_reg2 (21h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 20. ctrl_reg3 (22h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 21. ctrl_reg3 (22h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 22. data signal on int pad control bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 23. status_reg (27h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 24. status_reg (27h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 25. out_x (29h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 26. out_y (2bh) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 27. out_z (2dh) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 28. ff_wu_cfg (30h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 29. ff_wu_cfg (30h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 30. ff_wu_src (31h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 31. ff_wu_src (31h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 32. ff_wu_ths (32h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 33. ff_wu_ths (32h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 34. ff_wu_duration (33h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 35. ff_wu_duration (33h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 36. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
lis33de list of figures doc id 15596 rev 1 5/31 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. spi slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4. i2c slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. lis33de electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 6. read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 7. spi read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 8. multiple bytes spi read protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 9. spi write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 10. multiple bytes spi write protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 11. spi read protocol in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 12. lga 16: mechanical data and package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
block diagram and pin description lis33de 6/31 doc id 15596 rev 1 1 block diagram and pin description 1.1 block diagram figure 1. block diagram 1.2 pin description figure 2. pin connection charge amplifier mux y+ z+ y- z- a x+ x- i 2 c spi cs scl/spc sda/sdo/sdi sdo control logic & interrupt gen. int clock trimming circuits reference self test control logic a/d converter (top view) direction of the detectable accelerations 1 5 9 13 (bottom view) y 1 x z pin 1 indicator
lis33de block diagram and pin description doc id 15596 rev 1 7/31 table 2. pin description pin# name function 1 vdd_io power supply for i/o pins 2 nc not connected 3 nc not connected 4 scl spc i 2 c serial clock (scl) spi serial port clock (spc) 5 gnd 0 v supply 6 sda sdi sdo i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) 7sdo spi serial data output i 2 c less significant bit of the device address 8cs spi enable i 2 c/spi mode selection (1: i 2 c mode; 0: spi enabled) 9 reserved leave unconnected 10 reserved connect to gnd 11 int inertial interrupt 12 gnd 0 v supply 13 gnd 0 v supply 14 vdd power supply 15 reserved connect to vdd 16 gnd 0v supply
mechanical and electrical specifications lis33de 8/31 doc id 15596 rev 1 2 mechanical and electrical specifications 2.1 mechanical characteristics t = 25c unless otherwise noted table 3. mechanical characteristics @ vdd=2.5v (1) symbol parameter test conditions min. typ. (2) max. unit fs measurement range fs bit set to 0 (3) 2.0 2.3 g fs bit set to 1 9.2 dres device resolution fs bit set to 0 72 mg so sensitivity fs bit set to 0 15 18 21 mg/digit fs bit set to 1 61 72 83 tcso sensitivity change vs temperature fs bit set to 0 0.01 %/c ty o f f typical zero-g level offset accuracy (4) fs bit set to 0 60 mg fs bit set to 1 80 mg tcoff zero-g level change vs temperature max delta from 25c 0.5 mg/c vst self test output change (5),(6),(7) fs bit set to 0 stp bit used x axis -3 -19 -32 lsb fs bit set to 0 stp bit used y axis 31932lsb fs bit set to 0 stp bit used z axis -3 -19 -32 lsb bw system bandwidth (8) odr/2 hz top operating temperature range -40 +85 c wh product weight 20 mgram 1. the product is factory calibrated at 2.5 v. t he device can be used from 2.16 v to 3.6 v. 2. typical specificat ions are not guaranteed. 3. verified by wafer level test and measur ement of initial offset and sensitivity. 4. typical zero-g level offset value after msl3 preconditioning. 5. if stm bit is used, values change in sign for all axes. 6. self test output changes with the power supply. ?self test output change? is defined as output[lsb] (self-test bit on ctrl_reg1=1) -output[lsb] (self-test bit on ctrl_reg1=0) . 1lsb=4.6g/256 at 8bit representation, 2.3g full-scale. 7. output data reach 99% of final value after 3/od r when enabling self-test mode due to device filtering. 8. odr is output data rate. refer to table 4 for specifications.
lis33de mechanical and electrical specifications doc id 15596 rev 1 9/31 2.2 electrical characteristics t = 25c unless otherwise noted table 4. electrical characteristics @ vdd=2.5v (1) symbol parameter test conditions min. typ. (2) max. unit vdd supply voltage 2.16 2.5 3.6 v vdd_io i/o pins supply voltage (3) 1.71 vdd+0.1 v idd supply current t = 25c, odr=100 hz 0.3 0.45 ma iddpdn current consumption in power-down mode t = 25c 1 5 a vih digital high level input voltage 0.8*vdd _io v vil digital low level input voltage 0.2*vdd _io v voh high level output voltage 0.9*vdd _io v vol low level output voltage 0.1*vdd _io v odr output data rate dr=0 100 hz dr=1 400 bw system bandwidth (4) odr/2 hz ton turn-on time (5) 3/odr s top operating temperature range -40 +85 c 1. the product is factory calibrated at 2.5v. t he device can be used from 2.16v to 3.6v. 2. typical specification are not guaranteed. 3. it is possible to remove vdd maintaining vdd_io withou t blocking the communication busse s, in this condition the measurement chain is powered off. 4. filter cut-off frequency. 5. time to obtain valid data after exiting power-down mode.
mechanical and electrical specifications lis33de 10/31 doc id 15596 rev 1 2.3 communication interface characteristics 2.3.1 spi - serial peripheral interface subject to general operating conditions for vdd and top. figure 3. spi slave timing diagram (a) 3. when no communication is on-going, data on cs, spc, sdi and sdo are driven by internal pull-up resistors table 5. spi slave timing values symbol parameter value (1) 1. values are guaranteed at 10 mhz clock frequenc y for spi with both 4 and 3 wires, based on characterization results, not tested in production unit min max tc(spc) spi clock cycle 100 ns fc(spc) spi clock frequency 10 mhz tsu(cs) cs setup time 5 ns th(cs) cs hold time 8 tsu(si) sdi input setup time 5 th(si) sdi input hold time 15 tv(so) sdo valid output time 50 th(so) sdo output hold time 6 tdis(so) sdo output disable time 50 a. measurement points are done at 0.2vdd_io and 0.8vdd_io, for both input and output port spc cs sdi sdo t su(cs) t v(so) t h(so) t h(si) t su(si) t h(cs) t dis(so) t c(spc) msb in msb out lsb out lsb in (3) (3) (3) (3) (3) (3) (3) (3)
lis33de mechanical and electrical specifications doc id 15596 rev 1 11/31 2.3.2 i 2 c - inter ic control interface subject to general operating conditions for vdd and top. figure 4. i 2 c slave timing diagram (b) table 6. i 2 c slave timing values symbol parameter i 2 c standard mode (1) i 2 c fast mode (1) unit min. max. min. max. f (scl) scl clock frequency 0 100 0 400 khz t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0.01 3.45 0.01 0.9 s t r(sda) t r(scl) sda and scl rise time 1000 20 + 0.1c b ( 2) 300 ns t f(sda) t f(scl) sda and scl fall time 300 20 + 0.1c b (2) 300 t h(st) start condition hold time 4 0.6 s t su(sr) repeated start condition setup time 4.7 0.6 t su(sp) stop condition setup time 4 0.6 t w(sp:sr) bus free time between stop and start condition 4.7 1.3 1. data based on standard i 2 c protocol requirement, not tested in production 2. cb = total capacitance of one bus line, in pf b. measurement points are done at 0.2vdd_io and 0.8vdd_io, for both ports sd a scl t f(sda) t su(sp) t w(scll) t su(sda) t r(sda) t su(sr) t h(st) t w(sclh) t h(sda) t r(scl) t f(scl) t w(sp:sr) start repeated start stop start
mechanical and electrical specifications lis33de 12/31 doc id 15596 rev 1 2.4 absolute maximum ratings stresses above those listed as ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. note: supply voltage on any pin should never exceed 6.0 v table 7. absolute maximum ratings symbol ratings maximum value unit vdd supply voltage -0.3 to 6 v vdd_io i/o pins supply voltage -0.3 to 6 v vin input voltage on any control pin (cs, scl/spc, sda/sdi/sdo) -0.3 to vdd_io +0.3 v a pow acceleration (any axis, powered, vdd=2.5v) 3000g for 0.5 ms 10000g for 0.1 ms a unp acceleration (any axis, unpowered) 3000g for 0.5 ms 10000g for 0.1 ms t op operating temperature range -40 to +85 c t stg storage temperature range -40 to +125 c esd electrostatic discharge protection 0 - 2 (hbm) kv this is a mechanical shock sensitive device, improper handling can cause permanent damages to the part this is an esd sensitive device, improper handling can cause permanent damages to the part
lis33de mechanical and electrical specifications doc id 15596 rev 1 13/31 2.5 terminology 2.5.1 sensitivity sensitivity describes the gain of the sensor and can be determined e.g. by applying 1g acceleration to it. as the sensor can measur e dc accelerations this can be done easily by pointing the axis of interest towards the center of the earth, noting the output value, rotating the sensor by 180 degrees (pointing to the sky) and noting the output value again. by doing so, 1g acceleration is applied to the sensor. subtracting the larger output value from the smaller one and dividing the result by 2, leads to the actual sensitivity of the sensor. this value changes very little over temperature and also time. the sensitivity tolerance describes the range of sensitivities of a large population of sensors. 2.5.2 zero-g level zero-g level offset (tyoff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. a sensor in a steady state on a horizontal surface measure 0g in x axis and 0g in y axis wherea s the z axis measure 1g. the output is ideally in the middle of the dynamic range of the sensor (content of out registers 00h, data expressed as 2?s complement number). a deviat ion from ideal value in this case is called zero-g offset. offset is to some extent a result of stress to mems sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. offset changes little over temperature, see ?zero-g level change vs. temperature?. the zero-g level tolerance (tyoff) describes the standard deviation of the range of zero-g levels of a population of sensors. 2.5.3 self test self test allows to check the sensor functionality without moving it. the self test function is off when the self-test bit of ctrl_reg1 (control register 1) is programmed to ?0?. when the self-test bit of ctrl_reg1 is programmed to ?1? an actuation force is applied to the sensor, simulating a definite input acceleration. in this case the sensor outputs exhibit a change in their dc levels which are relate d to the selected full scale through the device sensitivity. when self test is activated, the device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test-force. if the output signals change within the amplitude specified inside table 3 , then the sensor is working properly and the parameters of the interface chip are within the defined specifications.
functionality lis33de 14/31 doc id 15596 rev 1 3 functionality the lis33de is an ultracompact, low-power, digital output 3-axis linear accelerometer packaged in a lga package. the complete device includes a sensing element and an ic interface able to take the information from the sensing element and to provide a signal to the external world through an i 2 c/spi serial interface. 3.1 sensing element a proprietary process is used to create a surface micro-machined accelerometer. the technology allows to carry out suspended s ilicon structures which are attached to the substrate in a few points called anchors and are free to move in the direction of the sensed acceleration. to be compatible with the traditional packaging techniques a cap is placed on top of the sensing element to avoid blocking the moving parts during the moulding phase of the plastic encapsulation. when an acceleration is applied to the sensor the proof mass displaces from its nominal position, causing an imbalance in the capacit ive half-bridge. this imbalance is measured using charge integration in response to a voltage pulse applied to the capacitor. at steady state the nominal value of the capacitors are few pf and when an acceleration is applied the maximum variation of the capacitive load is in ff range. 3.2 ic interface the complete measurement chain is composed by a low-noise capacitive amplifier which converts the capacitive unbalancing of the mems sensor into an analog voltage that is finally available to the user by analog-to-digital converters. the acceleration data may be accessed through an i 2 c/spi interface thus making the device particularly suitable for direct interfacing with a microcontroller. the lis33de features a data-ready signal (rdy) which indicates when a new set of measured acceleration data is available thus simplifying data synchronization in the digital system that uses the device. the lis33de may also be configured to generate an inertial wake-up and free-fall interrupt signal accordingly to a programmed acceleration event along the enabled axes. 3.3 factory calibration the ic interface is factory calibrated for sensitivity (so) and zero-g level (tyoff). the trimming values are stored inside the device in a non volatile memory. any time the device is turned on, the trimming parameters are downloaded into the registers to be used during the normal operation. this allows to use the device without further calibration.
lis33de application hints doc id 15596 rev 1 15/31 4 application hints figure 5. lis33de electrical connection the device core is supplied through vdd line while the i/o pads are supplied through vdd_io line. power supply decoupling capacitors (100 nf ceramic, 10 f al) should be placed as near as possible to the pin 14 of the device (common design practice). all the voltage and ground supplies must be present at the same time to have proper behavior of the ic (refer to figure 5 ). it is possible to re move vdd maintaining vdd_io without blocking the communication bus, in this condition the measurement chain is powered off. the functionality of the device and the measured acceleration data is selectable and accessible through the i 2 c/spi interface.when using the i 2 c, cs must be tied high. the functions, the threshold and the timing of the interrupt pin (int) can be completely programmed by the user through the i 2 c/spi interface. 4.1 soldering information the lga package is compliant with the ecopack?, rohs and ?green? standard. it is qualified for soldering heat resist ance according to jedec j-std-020c. leave ?pin 1 indicator? unconnected during soldering. land pattern and soldering recommendations are available at www.st.com/mems . cs 10uf vdd 100nf gnd vdd_io sdo sda/sdi/sdo int scl/spc digital signal from/to signal controller.signal?s levels are defined by proper selection of vdd_io 1 5 8 13 top view 6 9 14 16 9 5
digital interfaces lis33de 16/31 doc id 15596 rev 1 5 digital interfaces the registers embedded inside the lis33de may be accessed through both the i 2 c and spi serial interfaces. the latter may be sw configured to operate either in 3-wire or 4-wire interface mode. the serial interfaces are mapped onto the same pads. to select/exploit the i 2 c interface, cs line must be tied high (i.e connected to vdd_io). 5.1 i 2 c serial interface the lis33de i 2 c is a bus slave. the i 2 c is employed to write data into registers whose content can also be read back. the relevant i 2 c terminology is given in the table below. there are two signals associated with the i 2 c bus: the serial clock line (scl) and the serial data line (sda). the latter is a bidirectiona l line used for sending and receiving the data to/from the interface. both the lines are connected to vdd_io through a pull-up resistor embedded inside the lis33de. when the bus is free both the lines are high. the i 2 c interface is compliant wit h fast mode (400 khz) i 2 c standards as well as with the normal mode. table 8. serial interface pin description pin name pin description cs spi enable i 2 c/spi mode selection (1: i 2 c mode; 0: spi enabled) scl/spc i 2 c serial clock (scl) spi serial port clock (spc) sda/sdi/sdo i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) sdo spi serial data output (sdo) table 9. serial interface pin description term description transmitter the device which sends data to the bus receiver the device which receives data from the bus master the device which initiates a transfer, generates clock signals and terminates a transfer slave the device addressed by the master
lis33de digital interfaces doc id 15596 rev 1 17/31 5.1.1 i 2 c operation the transaction on the bus is started through a start (st) signal. a start condition is defined as a high to low transition on the data line while the scl line is held high. after this has been transmitted by the master, the bus is considered busy. the next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. when an address is sent, each device in the system compares the first seven bits after a start condition with its address. if they match, the device considers itself addressed by the master. the slave address (sad) associated to the lis33de is 001110xb. sdo pad can be used to modify less significant bit of the device addr ess. if sdo pad is connected to voltage supply lsb is ?1? (address 0011101b) else if sdo pad is connected to ground lsb value is ?0? (address 0011100b). this solution permits to connect and address two different accelerometers to the same i 2 c lines. data transfer with acknowledge is mandatory. the transmitter must release the sda line during the acknowledge pulse. the receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock pulse. a receiver which has been addressed is obliged to generate an acknowledge after each byte of data has been received. the i 2 c embedded inside the lis33de behaves like a slave device and the following protocol must be adhered to. after the start condition (st) a slave address is sent, once a slave acknowledge (sak) has bee n returned, a 8-bit sub-addre ss is transmitte d: the 7 lsb represent the actual register address while the msb enables address auto increment. if the msb of the sub field is 1, the sub (register address) is automatically incremented to allow multiple data read/write. the slave address is completed with a read/write bit. if the bit is ?1? (read), a repeated start (sr) condition is issued after the two sub-address bytes; if the bit is ?0? (write) the master will transmit to the slave with direction unchanged. table 10. transfer when master is writing one byte to slave table 11. transfer when master is writing multiple bytes to slave: table 12. transfer when master is receiving (reading) one byte of data from slave: master st sad + w sub data sp slave sak sak sak master st sad + w sub data data sp slave sak sak sak sak master st sad + w sub sr sad + r nmak sp slave sak sak sak data table 13. transfer when master is receiving (reading) one byte of data from slave master st sad + w sub sr sad + r nmak sp slave sak sak sak data
digital interfaces lis33de 18/31 doc id 15596 rev 1 data are transmitted in byte format (data). each data transfer contains 8 bits. the number of bytes transferred per transfer is unlimited. data is transferred with the most significant bit (msb) first. if a receiver can?t receive another complete byte of data until it has performed some other function, it can hold the clock line, scl low to force the transmitter into a wait state. data transfer only continues when the receiver is ready for another byte and releases the data line. if a slave receiver doesn?t acknowledge the slave address (i.e. it is not able to receive because it is performing some real time function) the data line must be left high by the slave. the master can then abort the transfer. a low to high transition on the sda line while the scl line is high is defined as a stop condition. each data transfer must be terminated by the generation of a stop (sp) condition. in order to read multiple bytes, it is necessary to assert the most significant bit of the sub- address field. in other words, sub(7) must be equal to 1 while sub(6-0) represents the address of first register to be read. in the presented communication format mak is master acknowledge and nmak is no master acknowledge. 5.2 spi bus interface the lis33de spi is a bus slave. the spi allows to write and read the registers of the device. the serial interface interacts with the outside world with 4 wires: cs , spc , sdi and sdo . figure 6. read and write protocol cs is the serial port enable and it is controlled by the spi master. it goes low at the start of the transmission and goes back high at the end. spc is the serial port clock and it is controlled by the spi master. it is stopped high when cs is high (no transmission). sdi and sdo are respectively the serial port data input and output. those lines are driven at the falling edge of spc and should be captured at the rising edge of spc . both the read register and write register commands are completed in 16 clock pulses or in multiple of 8 in case of multiple bytes read/wr ite. bit duration is the time between two falling edges of spc . the first bit (bit 0) starts at the first falling edge of spc after the falling edge table 14. transfer when master is receiving (reading) multiple bytes of data from slave master st sad+w sub sr sad+r mak mak nmak sp slave sak sak sak data data data cs spc sdi sdo rw ad5 ad4 ad3 ad2 ad1 ad0 di7di6di5di4di3di2di1di0 do7do6do5do4do3do2do1do0 ms
lis33de digital interfaces doc id 15596 rev 1 19/31 of cs while the last bit (bit 15, bit 23, ...) starts at the last falling edge of spc just before the rising edge of cs . bit 0 : rw bit. when 0, the data di(7:0) is written into the device. when 1, the data do(7:0) from the device is read. in la tter case, the chip will drives sdo at the start of bit 8. bit 1 : ms bit. when 0, the address will remains unchanged in mult iple read/write commands. when 1, the address is auto incremented in multiple read/write commands. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (write mode). this is the data that is written into the device (msb first). bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). in multiple read/write commands further blocks of 8 clock periods are added. when ms bit is 0 the address used to read/write data remains the same for every block. when ms bit is 1 the address used to read/write data is incremented at every block. the function and the behavior of sdi and sdo remain unchanged. 5.2.1 spi read figure 7. spi read protocol the spi read command is performed with 16 clock pulses. multiple byte read command is performed adding blocks of 8 clock pulses at the previous one. bit 0 : read bit. the value is 1. bit 1 : ms bit. when 0 do not increment address, when 1 increment address in multiple reading. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). bit 16-... : data do(...-8). further da ta in multiple byte reading. cs spc sdi sdo rw do7 do6 do5 do4 do3 do2 do1 do0 ad5 ad4 ad3 ad2 ad1 ad0 ms
digital interfaces lis33de 20/31 doc id 15596 rev 1 figure 8. multiple bytes spi read protocol (2 bytes example) 5.2.2 spi write figure 9. spi write protocol the spi write command is performed with 16 cl ock pulses. multiple by te write command is performed adding blocks of 8 clock pulses at the previous one. bit 0 : write bit. the value is 0. bit 1 : ms bit. when 0 do not increment address, when 1 increment address in multiple writing. bit 2 -7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (write mode). this is the data that is written inside the device (msb first). bit 16-... : data di(...-8). further data in multiple byte writing. figure 10. multiple bytes spi write protocol (2 bytes example) cs spc sdi sdo rw do7do6do5do4do3do2do1do0 ad5 ad4 ad3 ad2 ad1 ad0 do15 do14 do13 do12 do11 do10 do9 do8 ms cs spc sdi rw di7 di6 di5 di4 di3 di2 di1 di0 ad5 ad4 ad3 ad2 ad1 ad0 ms cs spc sdi rw ad5 ad4 ad3 ad2 ad1 ad0 di7 di6 di5 di4 di3 di2 di1 di0 di15 di14 di13 di12 di11 di10 di9 di8 ms
lis33de digital interfaces doc id 15596 rev 1 21/31 5.2.3 spi read in 3-wires mode 3-wires mode is entered by setting to 1 bit sim (spi serial interface mode selection) in ctrl_reg2. figure 11. spi read protocol in 3-wires mode the spi read command is performed with 16 clock pulses: bit 0 : read bit. the value is 1. bit 1 : ms bit. when 0 do not increment address, when 1 increment address in multiple reading. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). multiple read command is also available in 3-wires mode. cs spc sdi/o rw do7 do6 do5 do4 do3 do2 do1 do0 ad5 ad4 ad3 ad2 ad1 ad0 ms
register mapping lis33de 22/31 doc id 15596 rev 1 6 register mapping the table given below provides a listing of the 8 bit registers embedded in the device and the related address: registers marked as reserved must not be changed. the writing to those registers may cause permanent damages to the device. the content of the registers that are loaded at boot should not be changed. they contain the factory calibration values. their content is automatically restored when the device is powered-up. table 15. register address map name type register address default comment hex binary reserved (do not modify) 00-1f reserved ctrl_reg1 rw 20 010 0000 00000111 ctrl_reg2 rw 21 010 0001 00000000 ctrl_reg3 rw 22 010 0010 00000000 reserved (do not modify) 23-26 reserved status_reg r 27 010 0111 00000000 -- r 28 010 1000 not used outx r 29 010 1001 output -- r 2a 010 1010 not used outy r 2b 010 1011 output -- r 2c 010 1100 not used outz r 2d 010 1101 output reserved (do not modify) 2e-2f reserved ff_wu_cfg rw 30 011 0000 00000000 ff_wu_src(ack) r 31 011 0001 00000000 ff_wu_ths rw 32 011 0010 00000010 ff_wu_duration rw 33 011 0011 00000000 reserved (do not modify) 34-3f reserved
lis33de register description doc id 15596 rev 1 23/31 7 register description the device contains a set of registers which are used to control its behavior and to retrieve acceleration data. the registers address, made of 7 bits, is used to identify them and to write the data through serial interface. 7.1 ctrl_reg1 (20h) table 16. ctrl_reg1 (20h) register table 17. ctrl_reg1 (20h) register description dr bit allows to select the data rate at which acceleration samples are produced. the default value is ?0? which corresponds to a data-rate of 100 hz. by changing the content of dr to ?1? the selected data-rate will be set equal to 400 hz. pd bit allows to turn the device out of power-down mode. the device is in power-down mode when pd= ?0? (default value after boot). the device is in normal mode when pd is set to ?1?. stp, stm bits are used to activate the self-test function. when the bit is set to one, an output change will occur to the device outputs (re fer to table 2 and 3 fo r specification) thus allowing to check the functionality of the whole measurement chain. zen bit enables the generation of data ready signal for z-axis meas urement channel when set to ?1?. the default value is ?1?. yen bit enables the generation of data ready signal for y-axis measurement channel when set to ?1?. the default value is ?1?. xen bit enables the generation of data ready signal for x-axis measurement channel when set to ?1?. the default value is ?1?. dr pd fs stp stm zen yen xen dr data rate selection. default value: 0 (0: 100 hz output data rate; 1: 400 hz output data rate) pd power down control. default value: 0 (0: power down mode; 1: active mode) fs full scale selection. default value: 0 (refer to table 2 for ty pical full scale value) stp, stm self test enable. default value: 0 (0: normal mode; 1: self test p, m enabled) zen z axis enable. default value: 1 (0: z axis disabled; 1: z axis enabled) yen y axis enable. default value: 1 (0: y axis disabled; 1: y axis enabled) xen x axis enable. default value: 1 (0: x axis disabled; 1: x axis enabled)
register description lis33de 24/31 doc id 15596 rev 1 7.2 ctrl_reg2 (21h) table 18. ctrl_reg2 (21h) register table 19. ctrl_reg2 (21h) register description sim bit selects the spi serial interface mode. when sim is ?0? (default value) the 4-wire interface mode is selected. the data coming from the device are sent to sdo pad. in 3-wire interface mode output data are sent to sda_sdi pad. boot bit is used to refresh the content of internal registers stored in the flash memory block. at the device power up the content of the flash memory block is transferred to the internal registers related to trimming functions to permit a good behavior of the device itself. if for any reason the content of trimming registers is changed it is sufficient to use this bit to restore correct values. when boot bit is set to ?1? the content of internal flash is copied inside corresponding internal registers and it is used to calibrate the device. these values are factory trimmed and they are different for every accelerometer. they permit a good behavior of the device and normally they have not to be changed. at the end of the boot process the boot bit is set again to ?0?. 7.3 ctrl_reg3 [interrupt ctrl register] (22h) sim boot 0 (1) 1. bit to be kept to ?0? for correct device functionality. 0 (1) 0 (1) 0 (1) 0 (1) 0 (1) sim spi serial interface mode selection. default value: 0 (0: 4-wire interface; 1: 3-wire interface) boot reboot memory content. default value: 0 (0: normal mode; 1: reboot memory content) table 20. ctrl_reg3 (22h) register ihl 0 (1) 1. bit to be kept to ?0? for correct push-pull on interrupt pad (int). 0 (2) 2. bit to be kept to ?0? for correct device functionality. 0 (2) 0 (2) icfg2 icfg1 icfg0 table 21. ctrl_reg3 (22h) register description ihl interrupt active high, low. default value 0. (0: active high; 1: active low) icfg2- icfg0 data signal on int pad control bits. default value 000. (see table below)
lis33de register description doc id 15596 rev 1 25/31 7.4 status_reg (27h) table 22. data signal on int pad control bits icfg2 (1) 1. these are the allowed bit configurations. each other configuration may cause in correct device functionality. icfg1 (1) icfg0 (1) int pad 0 0 0 gnd 001 ff_wu 100 data ready table 23. status_reg (27h) register zxyor zor yor xor zyxda zda yda xda table 24. status_reg (27h) register description zyxor x, y and z axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data has overwritten the pr evious one before it is read) zor z axis data overrun. default value: 0 (0: no overrun has occurred; 1: a new data for the z-axis has overwritten the previous one) yor y axis data overrun. default value: 0 (0: no overrun has occurred; 1: a new data for the y-axis has overwritten the previous one) xor x axis data overrun. default value: 0 (0: no overrun has occurred; 1: a new data for the x-axis has overwritten the previous one) zyxda x, y and z axis new data available. default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) zda z axis new data available. default value: 0 (0: a new data for the z-axis is not yet available; 1: a new data for the z-axis is available) yda y axis new data available. default value: 0 (0: a new data for the y-axis is not yet available; 1: a new data for the y-axis is available) xda x axis new data available. default value: 0 (0: a new data for the x-axis is not yet available; 1: a new data for the x-axis is available)
register description lis33de 26/31 doc id 15596 rev 1 7.5 out_x (29h) x axis output data expressed as 2?s complement number. 7.6 out_y (2bh) y axis output data expressed as 2?s complement number. 7.7 out_z (2dh) z axis output data expressed as 2?s complement number. 7.8 ff_wu_cfg (30h) table 25. out_x (29h) register xd7 xd6 xd5 xd4 xd3 xd2 xd1 xd0 table 26. out_y (2bh) register yd7 yd6 yd5 yd4 yd3 yd2 yd1 yd0 table 27. out_z (2dh) register zd7 zd6 zd5 zd4 zd3 zd2 zd1 zd0 table 28. ff_wu_cfg (30h) register aoi lir zhie zlie yhie ylie xhie xlie table 29. ff_wu_cfg (30h) register description aoi and/or combination of interrupt events. default value: 0 (0: or combination of interrupt events; 1: and combination of interrupt events) lir latch interrupt request into ff_wu_src reg with the ff_wu_src reg cleared by reading ff_wu_src reg. default value: 0 (0: interrupt request not latched ; 1: interrupt request latched) zhie enable interrupt generation on z high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) zlie enable interrupt generation on z low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold)
lis33de register description doc id 15596 rev 1 27/31 7.9 ff_wu_src (31h) free-fall and wake-up source register. read only register. reading at this address clears ff_wu_src register and the ff, wu interrupt and allows the refreshment of data in the ff_wu_src register if the latched option is chosen. yhie enable interrupt generation on y high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) ylie enable interrupt generation on y low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) xhie enable interrupt generation on x high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) xlie enable interrupt generation on x low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) table 29. ff_wu_cfg (30h) register description (continued) table 30. ff_wu_src (31h) register -- ia zh zl yh yl xh xl table 31. ff_wu_src (31h) register description ia interrupt active. default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) zh z high. default value: 0 (0: no interrupt, 1: zh event has occurred) zl z low. default value: 0 (0: no interrupt; 1: zl event has occurred) yh y high. default value: 0 (0: no interrupt, 1: yh event has occurred) yl y low. default value: 0 (0: no interrupt, 1: yl event has occurred) xh x high. default value: 0 (0: no interrupt, 1: xh event has occurred) xl x low. default value: 0 (0: no interrupt, 1: xl event has occurred)
register description lis33de 28/31 doc id 15596 rev 1 7.10 ff_wu_ths (32h) most significant bit (dcrm) is used to select the resetting mode of the duration counter. if dcrm=0 counter is reset when the interrupt is no more active else if dcrm=1 duration counter is decremented. 7.11 ff_wu_duration (33h) duration register for free-fall/wake-up interrupt. duration step and maximum value depend on the odr chosen. step 2.5 msec, from 0 to 637.5 msec if odr=400 hz, else step 10 msec, from 0 to 2.55 sec when odr=100 hz. the counter used to implement duration function is blocked when lir=1 in configuration register and the interrupt event is verified. table 32. ff_wu_ths (32h) register dcrm ths6 ths5 ths4 ths3 ths2 ths1 ths0 table 33. ff_wu_ths (32h) register description dcrm resetting mode selection. default value: 0 (0: counter reset; 1: counter decremented) ths6, ths0 free-fall / wake-up threshold: default value: 000 0010 table 34. ff_wu_duration (33h) register d7 d6 d5 d4 d3 d2 d1 d0 table 35. ff_wu_duration (33h) register description d7-d0 duration value. default value: 0000 0000
lis33de package information doc id 15596 rev 1 29/31 8 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com. ecopack is an st trademark. figure 12. lga 16: mechanical data and package dimensions dimensions ref. mm inch min. typ. max. min. typ. max. a1 1.000 0.0 39 4 a2 0.7 8 50.0 3 0 9 a 3 0.200 0.007 9 d1 2. 8 50 3 .000 3 .150 0.1122 0.11 8 1 0.1240 e1 2. 8 50 3 .000 3 .150 0.1122 0.11 8 1 0.1240 l1 1.000 1.060 0.0 39 4 0.0417 l2 2.000 2.060 0.07 8 70.0 8 11 n1 0.500 0.01 9 7 n2 1.000 0.0 39 4 m 0.040 0.100 0.160 0.0016 0.00 39 0.006 3 p1 0. 8 75 0.0 3 44 p2 1.275 0.0502 t1 0.2 9 00. 3 50 0.410 0.0114 0.01 38 0.0161 t2 0.1 9 0 0.250 0. 3 10 0.0075 0.00 98 0.0122 d 0.150 0.005 9 k 0.050 0.0020 lga16 ( 3 x 3 x1.0mm) land grid array packa g e outline and 7 983 2 3 1 mechanical data
revision history lis33de 30/31 doc id 15596 rev 1 9 revision history table 36. document revision history date revision changes 17-apr-2009 1 initial release
lis33de doc id 15596 rev 1 31/31 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2009 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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